 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| C8051F230 ANALOG PERIPHERALS Two Comparators - Programmable Hysteresis - Configurable to Generate Interrupts or Reset VDD Monitor and Brown-out Detector ON-CHIP JTAG DEBUG - On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive In-System Debug (No Emulator Required!) - Provides Breakpoints, Single Stepping, Watchpoints, Stack Monitor - Inspect/Modify Memory and Registers - Superior Performance to Emulation Systems Using ICE-Chips, Target Pods, and Sockets - Low Cost, Complete Development Kit SUPPLY VOLTAGE ......................2.7V to 3.6V - Typical Operating Current: 9mA @ 25MHz - Typical Stop Mode Current: <0.1uA Temperature Range: -40C to +85C 48-Pin TQFP Package 8K Flash, 256 RAM, 48-Pin MCU PRELIMINARY 8051-COMPATIBLE C Core - Pipelined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz Clock - Expanded Interrupt Handler MEMORY - 256 Bytes Data RAM - 8k Bytes FLASH; In-System Programmable in 512 byte Sectors DIGITAL PERIPHERALS - 32 Port I/O (All 5V tolerant with High Sink Current) TM - Hardware SPI and UART Serial Ports Available Concurrently - Three General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator (2 to 16MHz) - External Oscillator: Crystal, RC, C, or Clock - Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Modes SPI is a trademark of Motorola, Inc. VDD VDD GND GND NC NC NC NC Analog/Digital Power Port 0 Latch UART Timer 0 Timer 1 Timer 2 P 0 M U X P 0 D r v P0.0/TX P0.1/RX P0.2//INT0 P0.3//INT1 P0.4/T0 P0.5/T1 P0.6/T2 P0.7/T2EX TCK TMS TDI TDO /RST JTAG Logic Debug HW Reset 8 0 5 1 C o r e 8kbyte FLASH 256 byte RAM Port 1 Latch CP0+ CP0 CP0 P 1 M U X P 1 D r v CP0CP1+ CP1 CP1 P1.0/CP0+ P1.1/CP0P1.2/CP0 P1.3/CP1+ P1.4/CP1P1.5/CP1 P1.6/SYSCLK P1.7 CP1SYSCLK MONEN VDD Monitor External Oscillator Circuit Internal Oscillator WDT Port 2 Latch SPI XTAL1 XTAL2 SFR Bus P 2 M U X P 2 D r v P 3 System Clock P2.0/SCK P2.1/MISO P2.2/MOSI P2.3/NSS P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 3 Latch D r v 7.15.2002 C8051F230 8K Flash, 256 RAM, 48-Pin MCU PRELIMINARY SELECTED ELECTRICAL SPECIFICATIONS TA = -40C to +85C, VDD = 2.7V unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX GLOBAL CHARACTERISTICS Supply Voltage 2.7 3.6 Supply Current (CPU Clock=25MHz 9 active) Clock=1MHz 0.4 Clock=32kHz; VDD Monitor Disabled 11 Supply Current (shutdown) Oscillator not running; VDD Monitor 10 Enabled Oscillator not running; VDD Monitor 0.1 Disabled Clock Frequency Range DC 25 COMPARATORS Supply Current (each comparator) 1.5 Response Time (CP+) - (CP-) = 100mV 4.0 UNITS V mA mA A A A MHz A s PACKAGE INFORMATION D D1 C8051F226DK DEVELOPMENT KIT MIN NOM MAX (mm) (mm) (mm) A E1 E - - 1.20 0.15 A1 0.05 A2 0.95 1.00 1.05 b 48 PIN 1 IDENTIFIER A2 0.17 0.22 0.27 9.00 7.00 0.50 9.00 7.00 - D D1 1 e e E A b A1 E1 |
Price & Availability of C8051F230
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |